1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to the improvement of the arrangement of peripheral circuits and bonding pads on a semiconductor chip.
2. Description of the Prior Art
The layout of a semiconductor memory device such as a dynamic or static random access memory (RAM) is divided mainly into a regular pattern circuit area, a peripheral circuit area, and a bonding pad area. Provided in the regular circuit area are circuits repeated regularly in line with word lines and/or bit lines. For example, memory cells are arranged in line with the word lines and the bit lines, row decoders are arranged in line with the word lines, and sense amplifiers and column decoders are arranged in line with the bit lines. Contrary to the above, no word line and no bit line is provided in the peripheral circuit area. That is, irregular pattern circuits are provided in the peripheral circuit area. The layout for such a regular pattern circuit area, an irregular or peripheral circuit area, and a bonding pad area is important when considering a high capacity semiconductor device.
According to one prior art layout of a semiconductor memory device, two peripheral circuit areas are provided on both sides of a regular circuit area. Further provided outside of the peripheral circuit areas are bonding pad areas. In this case, the peripheral circuit areas have to be connected directly or indirectly to each pad of the bonding pad areas. Therefore, one of the peripheral circuit areas has to somehow be connected to each pad located on the opposite side thereof, and vice versa. In this case, one peripheral circuit is connected directly to a power supply pad and some pads located on the opposite side thereof, and via the other peripheral circuit is connected to the other signal pads located on the opposite side thereof. As a result, the total line width of the signal lines and power supply lines linking the peripheral circuits and the pads and bypassing the regular circuit area becomes large, thereby reducing the area of the regular pattern circuit area, which is disadvantageous when trying to provide high capacity.
In addition, when the above-mentioned device is mounted on a cerdip or plastic package, some of the bonding posts of the package may be superimposed on the others, in order to reduce the capacitances of the connections between the bonding pads of the device and the bonding posts of the package. This reduces the entire area of the device, thereby reducing the area of the regular pattern circuit area, which is also disadvantageous to providing high capacity.
Further, there are many types of packages. For example, from a viewpoint of shapes, there are DIP's, leadless packages, flat packages, and the like, and from a viewpoint of materials and sealed states, there are metal sealed packages, cerdip packages, plastic packages, and the like. The configuration of the bonding posts of a package depends upon the type of package. However, in a semiconductor device, each pad has a purpose different from that of the other pads. Therefore, when a semiconductor device is designed for a certain type of package, such a semiconductor device may not be mounted in another type of package, due to the different arrangement of the bonding posts of the package. If such a semiconductor device is forced into another type of package, the connections linking the bonding pads and the bonding posts become very long, thereby reducing the cavity of the package and increasing the capacitance of the connections. Also, wire-bonding operations for the above-mentioned connections become difficult, thereby increasing the manufacturing cost.